1. Field of the Invention
The present invention relates to a MOS transistor having an electrostatic protection function, and also relates to a semiconductor integrated circuit apparatus having this MOS transistor.
2. Description of Related Art
In an input/output circuit of an integrated circuit (IC), a MOS transistor having an electrostatic protection function is used in order to prevent an electrostatic breakdown caused by an electrostatic surge applied to the input or output terminal.
FIG. 6 is a section view schematically showing the structure of a conventional NMOS transistor having an electrostatic protection function. FIG. 7 is an equivalent circuit diagram of the NMOS transistor shown in FIG. 6.
The NMOS transistor in FIG. 6 is separated, as an element, by a field oxide film 62 formed on the surface of a P-type semiconductor substrate 61. This NMOS transistor is provided on the outermost layer portion of the P-type semiconductor substrate 61 with an N+-type (high concentration N type) drain region 63, an annular N+-type source region 64 surrounding the periphery of the N+-type drain region 63 with a predetermined distance provided between the N+-type drain region 63 and the N+-type source region 64, an annular N−-type (low concentration N type) impurity region 65 surrounding the N+-type drain region 63 adjacent to the outer periphery thereof, and an annular P+-type (high concentration P type) impurity region 66 surrounding the N+-type source region 64 adjacent to the outer periphery thereof. A LOCOS 67 is formed on the N−-type impurity region 65. A gate oxide film 68 is formed in the channel region between the N+-type source region 64 and the N−-type impurity region 65. The inner peripheral portion of the gate oxide film 68 is positioned on the LOCOS 67. A gate electrode 69 is formed on the gate oxide film 68, and a drain electrode, a source electrode and a backgate electrode are respectively connected to the N+-type drain region 63, the N+-type source region 64 and the P+-type impurity region 66.
In the structure above-mentioned, parasitic resistance components 71, 72 are respectively generated in the P-type semiconductor substrate 61 and the N−-type impurity region 65. Further, the N−-type impurity region 65, the P-type semiconductor substrate 61 and the N+-type source region 64, form an NPN-type parasitic transistor 73 with the N−-type impurity region 65, the P-type semiconductor substrate 61 and the N+-type source region 64 respectively serving as a collector, a base and an emitter. Further, a PN junction by the P-type semiconductor substrate 61 and the N+-type drain region 63 forms a parasitic diode 74.
For example, when the NMOS transistor shown in FIG. 6 is used in an output circuit, the gate electrode 69 is connected to an internal circuit, and an output terminal is connected to the drain electrode with both the source electrode and the backgate electrode grounded. In such a case, a negative electrostatic surge applied to the output terminal, is escaped through the parasitic diode 74 with the NMOS transistor turned OFF. However, even though a positive electrostatic surge is applied to the output terminal, the NMOS transistor and the parasitic transistor 73 remain OFF. Accordingly, there is no route through which the positive electrostatic surge is escaped. Therefore, when a positive electrostatic surge exceeding the electrostatic breakdown voltage of the NMOS transistor, is applied to the output terminal (drain electrode), the NMOS transistor is broken at its part between the drain and the gate or between the drain and the source.